Jan Decaluwe <jan@jandecaluwe.com> [Sun, 06 May 2012 14:59:24 +0200] rev 1209
clarified synthesis
Jan Decaluwe <jan@jandecaluwe.com> [Sun, 06 May 2012 09:59:31 +0200] rev 1208
break up the modeling chapter in three
Mark high level clearly as separate from synthesis
Jan Decaluwe <jan@jandecaluwe.com> [Wed, 25 Apr 2012 21:25:04 +0200] rev 1207
Implemented and documented timescale attribute for VCD output
Jan Decaluwe <jan@jandecaluwe.com> [Wed, 18 Apr 2012 20:46:47 +0200] rev 1206
merged from 0.7
Jan Decaluwe <jan@jandecaluwe.com> [Wed, 18 Apr 2012 20:44:07 +0200] rev 1205
corrected Easics link
Jan Decaluwe <jan@jandecaluwe.com> [Mon, 12 Sep 2011 10:38:28 +0200] rev 1204
Merge development work
Christopher Felton <cfelton@ieee.org> [Fri, 22 Jul 2011 15:21:49 -0500] rev 1203
Added a cosimulation directory for modelsim
Christopher Felton <cfelton@ieee.org> [Fri, 22 Jul 2011 10:56:05 -0500] rev 1202
merged dev snapshots
Christopher Felton <cfelton@ieee.org> [Fri, 22 Jul 2011 10:42:49 -0500] rev 1201
Created a separate Makefile and VPI for modelsim to fix a memory leak issue.
Jan Decaluwe <jan@jandecaluwe.com> [Sun, 28 Aug 2011 17:08:49 +0200] rev 1200
pypy 1.6 benchmarks